Tenstorrent

Physical Design Engineer Timing

Automation Perl Python Tcl

You will drive timing convergence across blocks, partitions, sections, and top-level designs. You will generate and validate timing models, analyze violations, develop fixes, debug timing-flow issues, and support…

Chiplet Physical Design Engineer

RemoteNorth America

You will design and integrate chiplets into System-in-Package solutions. You will own synthesis, place-and-route, timing closure, ECO flows, and physical verification convergence for high-speed CPU designs on advanced…

GPU Tcl

AI FPGA Machine Learning SystemVerilog Uvm

Design Verification Lead AI Hardware

HybridNorth AmericaLead

Canada

You will lead verification strategy for next-generation AI hardware and guide verification engineers in validating AI core functionality and performance. You will architect verification plans, benchmark on-chip…

HybridEurope, North America

Director Customer Hardware Engineering

You will own technical relationships with strategic customers and FAEs, translate silicon needs into engineering specifications, and coordinate customer-specific hardware and software configurations. You will oversee…

AI Computer Vision Deep Learning Embedded Systems FPGA +4 skills

Field Application Engineer AI Software and Hardware

RemoteEurope

You will work directly with enterprise customers to understand technical challenges and deliver effective solutions through meetings, presentations, and workshops. You will collaborate with sales, provide customer…

AI Computer Vision Deep Learning Embedded Systems FPGA +4 skills

Field Application Engineer AI Software and Hardware

RemoteEurope

Serbia

You will work directly with enterprise customers in meetings, presentations, and workshops to understand technical challenges and provide effective AI solutions. You will collaborate with sales operations and product…

Physical Design Engineer

AI Machine Learning Perl Python Tcl

You will own the end-to-end physical implementation flow for high-performance CPU and AI/ML blocks, from synthesis through tapeout. You will optimize performance, power, and area, collaborate with RTL engineers, and…

HybridEurope, North America

Physical Design Engineer AI Accelerator IP

You will own end-to-end physical implementation for RISC-V CPU and AI accelerator IP blocks. You will perform synthesis, place-and-route, timing closure, and GDSII signoff, develop implementation collateral, and work…

AI Perl Python Tcl

Physical Design Engineer Die to Die Interface RTL to GDSII

RemoteNorth America

Automation PCIe Python SerDes Signal Integrity +1 skills

You will lead physical implementation and closure for high-speed die-to-die PHYs and controllers. You will own the RTL-to-GDSII flow, drive timing and verification, improve automation, and partner with chiplet and…

Physical Design Engineer PnR

You will execute synthesis, place-and-route, and static timing analysis for assigned AI SoC partitions. You will close EM/IR, maintain UPF power intent, drive equivalence and physical-verification signoff, and work…

Physical Design Engineer STA

Automation Perl Python Tcl

You will drive static timing analysis and closure for complex high-performance designs. You will debug constraints, optimize timing paths, create ECOs, develop automation scripts and closure methodologies, and…

HybridEurope, North America

Physical Design Methodology Engineer AI Hardware IP

You will develop, deploy, and own RTL-to-GDSII methodology for IP physical design. You will remove manual steps, make PPA exploration repeatable, build automation, qualify EDA releases, and establish flows for…

AI Automation CAD Perl Python +1 skills

HybridEurope, North AmericaStaff

Staff Design Verification Engineer AI Hardware

You will verify Tensix IP and subsystems through tape-out, own coverage closure, and build reusable verification environments. You will develop tests, debug RTL and testbench issues, and improve regression, CI/CD, EDA…

Bash CI/CD Linux Python SystemVerilog

Top Level Physical Design Engineer