Physical Design Methodology Engineer AI Hardware IP

You will develop, deploy, and own RTL-to-GDSII methodology for IP physical design. You will remove manual steps, make PPA exploration repeatable, build automation, qualify EDA releases, and establish flows for technology nodes, PDKs, and foundry targets. You will document flows and work with design teams and EDA vendors.

Responsibilities

• Develop, deploy, and own RTL-to-GDSII methodology
• Automate physical design flows and make PPA exploration repeatable
• Build AI-assisted flow-development practices
• Document flows for production use
• Establish flows for new technology nodes, PDKs, and foundry targets
• Qualify new EDA releases

Requirements

• 5+ years developing and supporting production physical design methodology or CAD flows
• Expertise with FusionCompiler, ICC2, Innovus, Genus, PrimeTime, RedHawk, Tcl, Python, and Perl
• Deep understanding of advanced-node methodology, UPF, CPF, clock tree synthesis, and signoff including EM/IR and DRC/LVS
• Experience establishing flows for new technology nodes, PDKs, or foundry targets
• Eligibility to access U.S. export-controlled technology