Top Level Physical Design Engineer

You will drive top-level implementation for complex AI and CPU system-on-chip designs. You will develop floorplans, power grids, and clock networks; manage chip-level design closure; and collaborate with architecture, RTL, and packaging stakeholders. You will optimize implementations for power, performance, area, and schedule.

Responsibilities

• Drive top-level implementation of AI and CPU system-on-chip designs
• Develop hierarchical floorplans, power grids, and clock networks
• Drive chip-level timing closure, EM/IR analysis, and physical verification
• Optimize chip implementations for power, performance, and area
• Collaborate with architecture, RTL, and packaging teams

Requirements

• 8+ years of top-level SoC physical design experience on complex multi-million-gate designs
• Expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution
• Experience with bump planning, RDL implementation, and multi-voltage domain designs
• Mastery of timing closure, EM/IR analysis, and chip-level physical verification
• Eligibility to access U.S. export-controlled technology