Staff Design Verification Engineer AI Hardware

You will verify Tensix IP and subsystems through tape-out, own coverage closure, and build reusable verification environments. You will develop tests, debug RTL and testbench issues, and improve regression, CI/CD, EDA compute, and reproducible verification infrastructure.

Responsibilities

• Verify Tensix IP and subsystems from planning through tape-out
• Own coverage goals and drive coverage closure
• Build and maintain reusable verification environments agents scoreboards and infrastructure
• Develop constrained-random and directed tests
• Close functional code and assertion coverage
• Debug issues across RTL and testbench
• Improve regression flows CI/CD integration EDA compute environments and reproducible setups

Requirements

• SystemVerilog
• Testbench development
• Microarchitecture verification
• Linux
• Python
• Bash
• Coverage-driven verification
• RTL debugging
• CI/CD
• Functional safety verification
• Formal verification
• SystemVerilog Assertions
• Formal property verification