Physical Design Engineer AI Accelerator IP

You will own end-to-end physical implementation for RISC-V CPU and AI accelerator IP blocks. You will perform synthesis, place-and-route, timing closure, and GDSII signoff, develop implementation collateral, and work with RTL owners to meet power, performance, and delivery targets.

Responsibilities

• Own physical implementation of IP blocks from synthesis through GDSII signoff
• Perform synthesis, place-and-route, and timing closure
• Close critical paths and meet power budgets with RTL owners
• Build floorplans, power grids, pin placement, and clocking strategies
• Deliver IP integration collateral and signoff reports

Requirements

• BS, MS, or PhD in EE, ECE, CE, or CS
• 5+ years of block-level or IP-centric physical design through tapeout
• Expertise with Innovus, ICC2, FusionCompiler, and PrimeTime
• Proficiency in Tcl, Python, and Perl
• Understanding of advanced-node challenges, low-power design, and signoff
• Experience with floorplanning, power grids, pin placement, clocking, and IP integration collateral