Physical Design Engineer Timing

You will drive timing convergence across blocks, partitions, sections, and top-level designs. You will generate and validate timing models, analyze violations, develop fixes, debug timing-flow issues, and support execution through tapeout. You will develop bottom-up constraints and automate timing and implementation workflows using scripting.

Responsibilities

• Drive timing convergence across blocks, partitions, sections, and top-level designs
• Generate and validate timing models and publish results
• Analyze timing violations and develop and propagate fixes
• Debug timing-flow issues and support execution through tapeout
• Develop and validate bottom-up constraints
• Partner on methodology updates and closure requirements
• Use Python, Perl, and Tcl for automation and flow development

Requirements

• 8+ years of experience in static timing analysis, timing closure, and advanced-node design implementation
• Experience with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff
• Skill in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners
• Ability to collaborate and communicate across distributed cross-functional engineering teams
• Eligibility to access U.S. export-controlled technology