Physical Design Engineer STA

You will drive static timing analysis and closure for complex high-performance designs. You will debug constraints, optimize timing paths, create ECOs, develop automation scripts and closure methodologies, and collaborate with logic, DFT, and physical design engineers to meet performance targets.

Responsibilities

• Drive static timing analysis and closure for high-performance designs
• Debug timing constraints and optimize timing paths
• Create ECOs and develop timing-closure strategies
• Develop automation scripts and timing methodologies
• Collaborate with logic, DFT, and physical design engineers

Requirements

• 7+ years of industry experience
• Proven record of successful tapeouts
• Knowledge of STA tools and techniques
• Knowledge of noise, crosstalk, and OCV analysis
• Proficiency in SDC constraints and ECO creation
• Proficiency in Python, Perl, and Tcl
• Familiarity with SPICE modeling and worst-case corner analysis