Physical Design Engineer PnR

You will execute synthesis, place-and-route, and static timing analysis for assigned AI SoC partitions. You will close EM/IR, maintain UPF power intent, drive equivalence and physical-verification signoff, and work with architecture, RTL, and DFT engineers to resolve implementation issues.

Responsibilities

• Execute synthesis, place-and-route, and static timing analysis for AI SoC partitions
• Close EM/IR and maintain UPF power intent
• Drive logical-equivalence and physical-verification signoff
• Resolve implementation and signoff issues with architecture, RTL, and DFT engineers

Requirements

• Experience with synthesis and place-and-route flows
• Experience with Synopsys Design Compiler, Fusion Compiler, and IC Compiler II
• Knowledge of UPF and multi-voltage power domains
• Knowledge of SoC interface IP integration
• Knowledge of DRC, LVS, EM/IR, LEC, Formality, CDC, PLL, DLL, OCC, or MBIST implementation