Physical Design Engineer Die to Die Interface RTL to GDSII

You will lead physical implementation and closure for high-speed die-to-die PHYs and controllers. You will own the RTL-to-GDSII flow, drive timing and verification, improve automation, and partner with chiplet and analog teams to resolve interface and tapeout issues.

Responsibilities

• Lead die-to-die physical implementation and closure from netlist to tapeout
• Own the RTL-to-GDSII physical design flow
• Drive static timing, signal-integrity, and physical-verification signoff
• Improve physical design methodologies, flows, and automation scripts
• Partner with chiplet and analog teams to resolve interface integration issues
• Apply EDA tools for implementation, analysis, and verification

Requirements

• 5+ years of ASIC physical design experience at 7nm or below
• Multiple successful tapeouts
• Experience owning full-chip implementation from RTL to GDSII
• Knowledge of high-speed D2D, PCIe, HBM, or SerDes interfaces
• Experience with STA, constraints, timing closure, signal integrity, and power integrity
• Proficiency in Tcl and Python
• Experience with Synopsys, Cadence, or Mentor EDA tools
• BS or MS in EE, CE, or a related field