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Emulation Test Engineer
You will lead pre-silicon validation on the Cadence Palladium platform. You will architect model builds and partitioning, maintain emulation and co-simulation environments, execute interface and memory validation…
ASIC Design Verification Engineer
You will develop verification strategies, test plans, methodologies, and SystemVerilog UVM environments for AI inference ASICs. You will create simulations and tests, drive coverage closure and root-cause analysis,…
Physical Design Engineer Timing
You will drive timing convergence across blocks, partitions, sections, and top-level designs. You will generate and validate timing models, analyze violations, develop fixes, debug timing-flow issues, and support…
Chiplet Physical Design Engineer
You will design and integrate chiplets into System-in-Package solutions. You will own synthesis, place-and-route, timing closure, ECO flows, and physical verification convergence for high-speed CPU designs on advanced…
Full Chip Physical Design Verification Engineer
You will drive full-chip signoff and physical-verification closure across advanced technology nodes. You will debug verification issues, collaborate with design and foundry stakeholders, and support successful…
Physical Design Engineer
You will own the end-to-end physical implementation flow for high-performance CPU and AI/ML blocks, from synthesis through tapeout. You will optimize performance, power, and area, collaborate with RTL engineers, and…
Physical Design CPU Methodology Engineer
You will define and drive implementation methodology, automation, and signoff infrastructure for high-performance CPU cores. You will establish RTL-to-GDS flows, develop automation and quality controls, improve PPA and…
Physical Design Engineer AI Accelerator IP
You will own end-to-end physical implementation for RISC-V CPU and AI accelerator IP blocks. You will perform synthesis, place-and-route, timing closure, and GDSII signoff, develop implementation collateral, and work…
Physical Design Engineer Die to Die Interface RTL to GDSII
You will lead physical implementation and closure for high-speed die-to-die PHYs and controllers. You will own the RTL-to-GDSII flow, drive timing and verification, improve automation, and partner with chiplet and…
Physical Design Engineer STA
You will drive static timing analysis and closure for complex high-performance designs. You will debug constraints, optimize timing paths, create ECOs, develop automation scripts and closure methodologies, and…
Physical Design Methodology Engineer AI Hardware IP
You will develop, deploy, and own RTL-to-GDSII methodology for IP physical design. You will remove manual steps, make PPA exploration repeatable, build automation, qualify EDA releases, and establish flows for…
System IP RTL Design Lead
You will lead the technical definition, selection, and integration of system IP for advanced SoCs. You will define requirements, specifications, interfaces, and integration methods; guide IP design through sign-off;…
AI ML Physical Design Flow Engineer
You will solve physical design challenges across advanced nodes and develop RTL-to-GDS methodologies. You will deploy AI and ML solutions in production flows, optimize EDA and CAD tools, and collaborate with…
FPGA Design Engineer
The FPGA Design Engineer at Evertz contributes to the development of advanced broadcast equipment used in real-time video and audio production, processing, and transport for Live sports production, News broadcasting,…
达摩院-高速互联验证工程师-计算技术
1. 负责高速互联模块和子系统的验证工作，涵盖验证计划制定、验证环境搭建、用例开发、覆盖率收敛与签核，保障验证目标按质按期达成 2. 基于 UVM 方法学搭建并持续演进可复用的验证平台，开发scoreboard、checker 等关键验证组件，构造随机的验证激励 3. 与架构、设计团队紧密协作，深入理解互联协议规范与微架构，将特性拆解为验证点，制定覆盖协议一致性、性能、异常场景的验证策略 4.…
CAD Back-end Lead
You will build, integrate, qualify, release, and support CAD flows across custom design, physical implementation, and physical verification. You will develop reusable frameworks, automate regression testing and quality…
Physical Design - SOC Top Lead
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose…
Physical Design Engineer - Timing Lead
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose…
Physical Design - CAD Lead
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose…
Applications Engineer - Silicon IP
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose…