ASIC Design Verification Engineer

You will develop verification strategies, test plans, methodologies, and SystemVerilog UVM environments for AI inference ASICs. You will create simulations and tests, drive coverage closure and root-cause analysis, work with FPGA and emulation groups on validation, and manage verification schedules, deliverables, and risks.

Responsibilities

• Develop and execute verification strategies for AI inference ASICs
• Define test plans and verification methodologies
• Lead development of SystemVerilog UVM verification environments
• Create simulation testbenches and directed and constrained-random tests
• Collaborate on functional coverage and closure
• Drive debugging and root-cause analysis for pre-silicon and post-silicon issues
• Work with FPGA and emulation groups on early hardware validation
• Manage verification schedules, deliverables, and risk mitigation plans

Requirements

• 8+ years of ASIC verification experience
• Expertise in SystemVerilog UVM and simulation tools
• Knowledge of verification planning, testbench development, and coverage-driven verification
• Experience with Cadence, Synopsys, or Mentor Graphics EDA tools
• Experience with debugging tools, waveform analysis, and Python, Perl, or Tcl scripting
• Familiarity with AI/ML accelerators, memory subsystems, and high-speed interconnects
• Track record of verifying complex ASIC designs
• Advanced degree in Electrical or Computer Engineering or related field
• Experience with hardware-software co-verification
• Knowledge of formal verification techniques
• Understanding of post-silicon validation and bring-up

Benefits

• Company-paid medical, dental, and vision insurance for employees and dependents
• Company-paid life and disability coverage
• Supplemental hospital, critical illness, and accident coverage
• Unlimited paid time off
• 13 paid company holidays
• Remote-first work
• Company-provided computer and home office setup
• Equity
• 401(k) matching from day one