System IP RTL Design Lead

You will lead the technical definition, selection, and integration of system IP for advanced SoCs. You will define requirements, specifications, interfaces, and integration methods; guide IP design through sign-off; and optimize performance, power, and area while meeting functional, security, and quality requirements.

Responsibilities

• Lead the definition, selection, and integration of internally and third-party developed IP, including MMUs, interrupt controllers, interconnects, memory controllers, and peripherals
• Define system-level requirements, IP specifications, interfaces, and integration methodologies
• Drive IP design through sign-off activities
• Ensure compliance with functional, security, and quality requirements
• Apply expertise in AXI, AHB, APB, PCIe, DDR, USB, Python, Tcl, UVM, and formal verification

Requirements

• 20+ years of expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration
• RTL design and debug experience using Verilog or SystemVerilog
• Experience with simulation, synthesis, lint, CDC, and power analysis
• Experience driving microarchitecture decisions, authoring design specifications, and optimizing PPA trade-offs
• Experience debugging complex logic in pre-silicon simulation, emulation, and post-silicon bring-up
• Ability to collaborate across architecture, design, verification, physical design, software, firmware, and external IP vendors
• Strong communication and engineering mentorship skills
• Eligibility to access U.S. export-controlled technology