Full Chip Physical Design Verification Engineer

You will drive full-chip signoff and physical-verification closure across advanced technology nodes. You will debug verification issues, collaborate with design and foundry stakeholders, and support successful tapeouts.

Responsibilities

• Lead physical-verification closure and full-chip signoff
• Perform DRC, LVS, ERC, and related verification
• Debug physical-verification issues using industry tools
• Collaborate with RTL, physical design, CAD, packaging, and foundry stakeholders
• Drive signoff toward successful tapeouts

Requirements

• BS or MS in Electrical or Electronics Engineering or a related field
• 7–14 years of CPU, IP, or SoC physical-verification experience
• DRC, LVS, ERC, PERC, Antenna, and DFM verification expertise
• Experience with Calibre, ICV, Pegasus, FC, or Innovus
• ESD planning, padring integration, bump or RDL strategy, and reliability-analysis knowledge
• Understanding of advanced nodes and FinFET design challenges
• Python and TCL scripting proficiency