Physical Design CPU Methodology Engineer

You will define and drive implementation methodology, automation, and signoff infrastructure for high-performance CPU cores. You will establish RTL-to-GDS flows, develop automation and quality controls, improve PPA and turnaround time, explore AI/ML-enabled physical-design tooling, and work across engineering disciplines to enable advanced-node implementation.

Responsibilities

• Define and own CPU physical-design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification
• Explore AI/ML-enabled physical-design tooling
• Begin synthesis and place-and-route of CPU partitions
• Develop the new program RM flow
• Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows
• Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams

Requirements

• 10+ years of ASIC, SoC, or CPU experience
• Experience with high-performance CPUs or similarly complex digital designs
• Expertise in RTL-to-GDS implementation and signoff
• Knowledge of timing closure, power optimization, signal integrity, EM/IR, extraction, and physical verification
• Experience owning physical-design methodology, automation, or CAD flows
• Tcl, Python, Perl, or similar scripting skills
• Ability to influence teams, mentor engineers, and drive standards