Emulation Test Engineer

You will lead pre-silicon validation on the Cadence Palladium platform. You will architect model builds and partitioning, maintain emulation and co-simulation environments, execute interface and memory validation plans, analyze performance and power, and work with Cadence to resolve tool issues.

Responsibilities

• Lead partitioning and compilation across a multi-rack Palladium environment
• Create and maintain hybrid emulation and co-simulation environments
• Enable software teams to boot OS images and run AI workloads on pre-silicon hardware
• Design and execute emulation test plans for high-speed interfaces and AI memory hierarchies
• Use dynamic power analysis and throughput monitors to identify performance bottlenecks
• Act as the technical contact for Cadence R&D

Requirements

• 8+ years of ASIC emulation or verification experience
• Experience with large-scale Cadence Palladium installations
• Cadence Palladium Z1, Z2, or Z3 expertise
• Experience with advanced clocking, ICE, and VIF flows
• Experience emulating multi-billion-gate designs
• Python, Tcl, and Bash automation skills
• Low-level firmware and kernel debugging skills
• Experience with Verdi, SimVision, and hardware-software co-debug tools
• SystemVerilog, Verilog, and C/C++ proficiency
• Knowledge of PCIe, DDR, and AMBA AXI/NoC

Benefits

• Fully company-paid medical, dental, and vision insurance for employees and dependents
• Company-paid life and disability coverage
• Supplemental hospital, critical illness, and accident coverage
• Unlimited paid time off
• 13 paid company holidays
• Company-provided computer and home office setup
• 401(k) with company matching from day one
• Equity