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Principal ASIC Design Engineer
You will define microarchitecture and deliver parameterized SystemVerilog RTL for critical ASIC IP blocks and subsystems. You will lead front-end signoff, optimize PPA, integrate interfaces and memory systems, improve…
Physical Design Engineer Backend
You will implement RTL-to-GDS physical designs for performance, power, and area. You will perform floorplanning, power planning, placement, clock-tree synthesis, routing, verification, and GDS delivery. You will…
Physical Implementation Engineer DFT
You will implement scan, BIST, BIRA, and DFT logic; plan package-level testing; and support DFT from synthesis through production. You will improve test and fault coverage, analyze quality-of-results trends, and…
平头哥-封装设计高级工程师-深圳
1、面向数据中心芯片产品（CPU/GPU/AI 加速器等），主导定制具备行业竞争力的高质量封装解决方案； 2、基于芯片应用场景与系统需求，牵头开展 Floorplan、Bump Matrix、Pinmap、Interposer、Substrate 的评估与设计，统筹 Chiplet 划分、Die-to-Die 互连等封装关键设计环节； 3、从设计、验证、NPI…
平头哥-封装设计高级工程师-上海
1、面向数据中心芯片产品（CPU/GPU/AI 加速器等），主导定制具备行业竞争力的高质量封装解决方案； 2、基于芯片应用场景与系统需求，牵头开展 Floorplan、Bump Matrix、Pinmap、Interposer、Substrate 的评估与设计，统筹 Chiplet 划分、Die-to-Die 互连等封装关键设计环节； 3、从设计、验证、NPI…
Physical Design Engineer - Frontend
You will implement RTL-to-GDS physical-design flows and optimize power, performance, and area. You will perform logic synthesis, clock-gating insertion, equivalence checking, functional ECO, static timing analysis,…
SoC/Top Design Engineer
You will design SoC top-level architecture and integrate RTL. You will integrate CPU, AI, and memory subsystems; define bus interconnects; manage clock, reset, and power domains; perform synthesis, timing, and power…
Software Engineer Compiler Kernel Optimization
You will own the performance of critical AI kernels in Furiosa-LLM. You will analyze serving workloads, identify bottlenecks, implement optimized TCL kernels, and develop scheduling and algorithmic techniques for…
Software Engineer AI Model Enablement and Inference
You will analyze model architectures, implement and optimize TCL kernels, and integrate models into Furiosa-LLM. You will validate correctness on NPUs, automate benchmarking and regression testing, evaluate…
Physical Design Engineer
You will synthesize, place, and route high-speed designs and integrate physical-design blocks into the full-chip architecture. You will perform physical verification, resolve DRC and LVS issues, conduct IR and EM…
Lead RTL Design Engineer
You will drive chip design from functional specification and microarchitecture through RTL development and synthesis. You will manage an external ASIC vendor, partner with physical design, verification, DFT, software,…
Hardware Design Verification Engineer
You will define and implement verification plans for blocks, IP, subsystems, and SoCs. You will build test benches, develop functional tests, drive verification closure through coverage metrics, debug design failures…
Emulation Test Engineer
You will lead pre-silicon validation on the Cadence Palladium platform. You will architect model builds and partitioning, maintain emulation and co-simulation environments, execute interface and memory validation…
ASIC Design Verification Engineer
You will develop verification strategies, test plans, methodologies, and SystemVerilog UVM environments for AI inference ASICs. You will create simulations and tests, drive coverage closure and root-cause analysis,…
Physical Design Engineer Timing
You will drive timing convergence across blocks, partitions, sections, and top-level designs. You will generate and validate timing models, analyze violations, develop fixes, debug timing-flow issues, and support…
Chiplet Physical Design Engineer
You will design and integrate chiplets into System-in-Package solutions. You will own synthesis, place-and-route, timing closure, ECO flows, and physical verification convergence for high-speed CPU designs on advanced…
Full Chip Physical Design Verification Engineer
You will drive full-chip signoff and physical-verification closure across advanced technology nodes. You will debug verification issues, collaborate with design and foundry stakeholders, and support successful…
Physical Design Engineer
You will own the end-to-end physical implementation flow for high-performance CPU and AI/ML blocks, from synthesis through tapeout. You will optimize performance, power, and area, collaborate with RTL engineers, and…
Physical Design CPU Methodology Engineer
You will define and drive implementation methodology, automation, and signoff infrastructure for high-performance CPU cores. You will establish RTL-to-GDS flows, develop automation and quality controls, improve PPA and…
Physical Design Engineer AI Accelerator IP
You will own end-to-end physical implementation for RISC-V CPU and AI accelerator IP blocks. You will perform synthesis, place-and-route, timing closure, and GDSII signoff, develop implementation collateral, and work…