Principal ASIC Design Engineer

You will define microarchitecture and deliver parameterized SystemVerilog RTL for critical ASIC IP blocks and subsystems. You will lead front-end signoff, optimize PPA, integrate interfaces and memory systems, improve design methodology and automation, collaborate on verification and performance correlation, and mentor junior engineers.

Responsibilities

• Define and document microarchitecture for complex IP blocks and subsystems
• Deliver production-quality parameterized SystemVerilog RTL with defined interfaces, power and clock intent, and embedded assertions
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up
• Collaborate on floorplanning and timing closure
• Own PPA metrics and optimize microarchitecture to meet targets
• Architect and integrate interconnects, DMA engines, coherency logic, and HBM or DDR interfaces
• Engage IP vendors and internal stakeholders on integration
• Develop coding guidelines, reusable IP packaging, and signoff checklists
• Contribute Python, Tcl, Make, and CI automation flows
• Define verification test plans and reference models
• Correlate architecture and performance models against RTL
• Support bring-up, post-silicon debug, and customer engagements
• Mentor junior engineers and lead design reviews

Requirements

• BS/MS in EE/CE or related field
• 8+ years of ASIC or SoC RTL design experience
• Experience leading designs from specification through microarchitecture, RTL, and signoff
• SystemVerilog RTL expertise
• Experience with clocking, resets, CDC/RDC handling, and protocol correctness
• Experience with lint, CDC, synthesis/STA, and DFT tools
• Hands-on expertise with at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, or high-throughput datapaths
• Cross-functional communication skills

Benefits

• Equity
• Comprehensive benefits