SoC/Top Design Engineer

You will design SoC top-level architecture and integrate RTL. You will integrate CPU, AI, and memory subsystems; define bus interconnects; manage clock, reset, and power domains; perform synthesis, timing, and power analysis; collaborate on design closure and tape-out; and support DFT and functional verification.

Responsibilities

• Design SoC top-level architecture and perform RTL integration
• Integrate CPU, AI, and memory subsystems and define bus interconnects
• Manage clock, reset, power-domain controls, and verification environments
• Conduct synthesis, timing, and power analysis to optimize performance
• Collaborate with backend and verification teams to achieve design closure and tape-out
• Support DFT and functional verification activities

Requirements

• At least 5 years of RTL design and SoC integration experience
• Knowledge of Verilog, SystemVerilog, and AMBA protocols including AXI and AHB
• Proficiency with EDA tools
• Understanding of SoC design flow, including synthesis, P&R, STA, and ECO
• Experience with CPU, GPU, or NPU IP integration
• Expertise in low-power and high-speed design
• Familiarity with UVM-based verification environments
• Python or Tcl scripting skills
• Experience with Linux-based development environments