Hardware Design Verification Engineer

You will define and implement verification plans for blocks, IP, subsystems, and SoCs. You will build test benches, develop functional tests, drive verification closure through coverage metrics, debug design failures with the Design team, and collaborate with design, model, emulation, and silicon-validation teams.

Responsibilities

• Define and implement verification plans
• Build verification test benches
• Develop functional tests
• Drive design verification to closure using coverage metrics
• Debug, root-cause, and resolve functional design failures
• Collaborate with design, model, emulation, and silicon-validation teams

Requirements

• 3+ years of block, IP, subsystem, or SoC verification using SystemVerilog and UVM methodologies
• EDA tools
• Python, TCL, Perl, or Shell scripting
• Design Verification infrastructure
• Full verification-cycle execution