Tenstorrent
Open positions
Senior Staff Engineer Design Verification System IP
You will own end-to-end verification of IOMMU IP, from understanding the specification through coverage closure. You will build verification environments, create test plans, debug regressions, analyze coverage, and…
Physical Design Engineer Timing
You will drive timing convergence across blocks, partitions, sections, and top-level designs. You will generate and validate timing models, analyze violations, develop fixes, debug timing-flow issues, and support…
Chiplet Physical Design Engineer
You will design and integrate chiplets into System-in-Package solutions. You will own synthesis, place-and-route, timing closure, ECO flows, and physical verification convergence for high-speed CPU designs on advanced…
Full Chip Physical Design Verification Engineer
You will drive full-chip signoff and physical-verification closure across advanced technology nodes. You will debug verification issues, collaborate with design and foundry stakeholders, and support successful…
Physical Design Engineer
You will own the end-to-end physical implementation flow for high-performance CPU and AI/ML blocks, from synthesis through tapeout. You will optimize performance, power, and area, collaborate with RTL engineers, and…
Physical Design CPU Methodology Engineer
You will define and drive implementation methodology, automation, and signoff infrastructure for high-performance CPU cores. You will establish RTL-to-GDS flows, develop automation and quality controls, improve PPA and…
Physical Design Engineer AI Accelerator IP
You will own end-to-end physical implementation for RISC-V CPU and AI accelerator IP blocks. You will perform synthesis, place-and-route, timing closure, and GDSII signoff, develop implementation collateral, and work…
Physical Design Engineer Die to Die Interface RTL to GDSII
You will lead physical implementation and closure for high-speed die-to-die PHYs and controllers. You will own the RTL-to-GDSII flow, drive timing and verification, improve automation, and partner with chiplet and…
Physical Design Engineer STA
You will drive static timing analysis and closure for complex high-performance designs. You will debug constraints, optimize timing paths, create ECOs, develop automation scripts and closure methodologies, and…
Physical Design Methodology Engineer AI Hardware IP
You will develop, deploy, and own RTL-to-GDSII methodology for IP physical design. You will remove manual steps, make PPA exploration repeatable, build automation, qualify EDA releases, and establish flows for…
System IP RTL Design Lead
You will lead the technical definition, selection, and integration of system IP for advanced SoCs. You will define requirements, specifications, interfaces, and integration methods; guide IP design through sign-off;…
AI ML Physical Design Flow Engineer
You will solve physical design challenges across advanced nodes and develop RTL-to-GDS methodologies. You will deploy AI and ML solutions in production flows, optimize EDA and CAD tools, and collaborate with…