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Tenstorrent

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9 jobs
Tenstorrent
last month

Senior Staff Engineer Design Verification System IP

HybridAPACStaff
India

You will own end-to-end verification of IOMMU IP, from understanding the specification through coverage closure. You will build verification environments, create test plans, debug regressions, analyze coverage, and…

Bash PCIe Perl Python SystemVerilog +2 skills
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Tenstorrent
last month

CPU Core Design Verification Manager

HybridAPAC
India

You will lead the Bangalore CPU Core Design Verification team and manage hiring, mentoring, performance management, and growth. You will own verification strategy and delivery, coordinate across sites, drive tapeout…

AI Performance Management Uvm
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Tenstorrent
last month

CPU Core Design Verification Testbench Lead

HybridNorth AmericaLead
United States

You will lead CPU core-level testbench development and evolve CVM-based verification infrastructure. You will plan functional verification, develop testbench components and stimulus, debug regressions, close coverage,…

AI Assembly C++ Python Root Cause Analysis +1 skills
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Tenstorrent
last month

Design Verification Lead AI Hardware

HybridNorth AmericaLead
Canada

You will lead verification strategy for next-generation AI hardware and guide verification engineers in validating AI core functionality and performance. You will architect verification plans, benchmark on-chip…

AI FPGA Machine Learning SystemVerilog Uvm
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Tenstorrent
last month

Front End Design Verification Engineer

RemoteEurope, North America

You will verify the fetch unit for next-generation high-performance RISC-V CPU cores. You will develop verification strategies and tests, debug complex failures, and validate instruction fetch, prediction, decode, and…

C++ Python SystemVerilog Uvm
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Tenstorrent
last month

Mid Core Design Verification Engineer

RemoteEurope, North AmericaMiddle
Spain

You will verify next-generation high-performance RISC-V CPU cores. You will develop verification strategies, test plans, and testbenches; create constrained-random tests, assertions, and coverage; debug RTL and…

C++ Python SystemVerilog Uvm
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Tenstorrent
last month

Senior Staff Engineer CPU Front-End Verification

HybridNorth AmericaStaff
United States

You will build and maintain UVM testbenches for CPU front-end units, create directed and constrained-random tests, and develop C++ reference models. You will execute verification plans, analyze coverage, and verify…

C++ SystemVerilog Uvm
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Tenstorrent
last month

Senior Staff Engineer SoC RTL Design

HybridNorth AmericaStaff

You will define, implement, and optimize custom IP blocks and SoC components for AI and compute workloads. You will make performance-aware design decisions, contribute to validation activities, and support backend…

AI FPGA Prototyping Uvm Verilog +1 skills
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Tenstorrent
last month

System IP RTL Design Lead

HybridAPACLead
India

You will lead the technical definition, selection, and integration of system IP for advanced SoCs. You will define requirements, specifications, interfaces, and integration methods; guide IP design through sign-off;…

Firmware PCIe Python Rtl SystemVerilog +3 skills
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