Senior Staff Engineer SoC RTL Design
Posted Updated
Description
You will define, implement, and optimize custom IP blocks and SoC components for AI and compute workloads. You will make performance-aware design decisions, contribute to validation activities, and support backend teams with synthesis and timing-closure awareness.
Responsibilities
- Define and implement custom IP blocks and SoC components
- Make performance-aware design decisions for compute, interconnect, or memory-heavy blocks
- Contribute to validation using emulation, FPGA prototyping, or UVM flows
- Support backend teams with synthesis and timing-closure awareness
Requirements
- Digital design expertise
- Computer architecture
- IP microarchitecture
- RTL development with Verilog or VHDL
- Full ASIC flow knowledge
- Power performance and area optimization
- On-chip fabric and interconnect design experience