Senior Staff Engineer CPU Front-End Verification

You will build and maintain UVM testbenches for CPU front-end units, create directed and constrained-random tests, and develop C++ reference models. You will execute verification plans, analyze coverage, and verify complex fetch, prediction, cache, and TLB edge cases.

Responsibilities

• Build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks
• Develop constrained-random and directed tests for speculation, redirects, fetch bubbles, and cache and TLB interactions
• Develop and maintain C++ reference models and predictors
• Execute verification plans and track functional and code coverage
• Verify edge cases and drive coverage closure

Requirements

• CPU front-end verification experience
• SystemVerilog
• UVM
• C++
• Unit-level testbench development
• Instruction fetch verification
• Branch prediction verification
• Instruction cache or TLB verification
• Transactor, predictor, and scoreboard development
• RTL debugging