Front End Design Verification Engineer

You will verify the fetch unit for next-generation high-performance RISC-V CPU cores. You will develop verification strategies and tests, debug complex failures, and validate instruction fetch, prediction, decode, and dispatch across workloads and corner cases.

Responsibilities

• Verify the CPU fetch unit and front-end logic
• Develop verification strategies and sophisticated tests
• Debug complex RTL and simulation failures
• Validate instruction fetch, prediction, decode, and dispatch behavior
• Partner with CPU architects, RTL designers, and verification engineers

Requirements

• 6+ years of design-verification experience for CPUs, SoCs, ASICs, or complex digital designs
• SystemVerilog and UVM experience
• Constrained-random testing, assertions, functional coverage, and testbench-development experience
• Understanding of CPU architecture and pipelines
• Experience debugging RTL and simulation failures
• C, C++, or Python programming skills