Positron AI
Open positions
Senior ASIC Design Engineer
You will lead the definition, implementation, and RTL signoff of critical ASIC and SoC IP blocks. You will own microarchitecture, PPA, integration, timing closure, and methodology improvements; collaborate across…
Senior Design for Test Engineer
You will own end-to-end DFT implementation for AI accelerators, from micro-architecture definition through tapeout and first-silicon bring-up. You will implement and integrate DFT logic in RTL and third-party IP,…
Principal ASIC Design Engineer
You will define microarchitecture and deliver parameterized SystemVerilog RTL for critical ASIC IP blocks and subsystems. You will lead front-end signoff, optimize PPA, integrate interfaces and memory systems, improve…
Emulation Test Engineer
You will lead pre-silicon validation on the Cadence Palladium platform. You will architect model builds and partitioning, maintain emulation and co-simulation environments, execute interface and memory validation…
Director of Silicon Validation
You will lead pre-silicon verification, hardware emulation, and post-silicon validation through tape-out and production. You will set verification strategy, build emulation and regression infrastructure, lead silicon…
Director of ASIC Design
You will lead design, development, verification, and execution for high-performance AI inference chips. You will define ASIC architecture, microarchitecture, and roadmaps; optimize power, performance, area, and memory…
ASIC Design Verification Engineer
You will develop verification strategies, test plans, methodologies, and SystemVerilog UVM environments for AI inference ASICs. You will create simulations and tests, drive coverage closure and root-cause analysis,…
ASIC Design Engineer
You will define microarchitecture and deliver parameterized SystemVerilog RTL for complex IP blocks and subsystems. You will lead signoff activities, optimize PPA, integrate interfaces and memory technologies, improve…