Senior ASIC Design Engineer

You will lead the definition, implementation, and RTL signoff of critical ASIC and SoC IP blocks. You will own microarchitecture, PPA, integration, timing closure, and methodology improvements; collaborate across engineering functions; and mentor junior engineers through design decisions and reviews.

Responsibilities

• Define and document microarchitecture for complex IP blocks and subsystems.
• Deliver parameterized SystemVerilog RTL with interfaces, power and clock intent, and assertions.
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up.
• Collaborate on floorplanning and timing closure.
• Own PPA metrics and drive microarchitectural optimizations.
• Architect and integrate interconnects, DMA engines, coherency logic, and memory interfaces.
• Engage IP vendors and internal stakeholders for integration.
• Develop coding guidelines, IP packaging, signoff checklists, and automation flows.
• Define test plans and reference models with Verification.
• Correlate architecture and performance models against RTL.
• Support bring-up, post-silicon debug, and customer engagements.
• Mentor junior engineers and lead design reviews.

Requirements

• BS/MS in EE/CE or a related field
• 8+ years of ASIC/SoC RTL design experience
• Microarchitecture
• SystemVerilog
• CDC/RDC
• Protocol design
• Lint
• Synthesis
• Static timing analysis
• DFT
• HBM or DDR
• PCIe or CXL
• AMBA AXI, ACE, or CHI
• Cache and memory hierarchy
• Datapath design
• AI/ML accelerator design
• Formal verification
• SystemVerilog Assertions
• Low-power design
• UPF or CPF
• cocotb or UVM
• RISC-V
• Coherence protocol
• COT flow

Benefits

• Equity
• Flexible work environment