ASIC Design Engineer

You will define microarchitecture and deliver parameterized SystemVerilog RTL for complex IP blocks and subsystems. You will lead signoff activities, optimize PPA, integrate interfaces and memory technologies, improve design methodology and automation, support validation and debugging, and guide junior engineers through design reviews and technical tradeoffs.

Responsibilities

• Define and document microarchitecture for complex IP blocks and subsystems
• Deliver parameterized SystemVerilog RTL with interfaces, power and clock intent, and assertions
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up
• Collaborate on floorplanning and timing closure
• Own PPA metrics and drive microarchitectural optimization
• Integrate interconnects, DMA engines, coherency logic, and memory interfaces
• Develop coding guidelines, reusable IP packaging, signoff checklists, and automation flows
• Partner on test plans, reference models, model correlation, bring-up, and post-silicon debugging
• Guide junior engineers and lead design reviews

Requirements

• 8+ years of ASIC or SoC RTL design experience
• Experience leading designs from specification through signoff
• SystemVerilog RTL expertise
• Experience with clocking, resets, CDC/RDC handling, and protocol correctness
• Experience with lint, CDC, synthesis, STA, and DFT tools
• Expertise in at least three of HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache or memory hierarchies, and high-throughput datapaths
• Cross-functional communication skills