Velaura AI, Inc.
Open positions
Functional Safety Architect
You will define functional safety goals, mechanisms, and fault-handling strategies for SoCs. You will lead safety analyses, establish safety processes, develop safety cases, embed requirements across hardware and…
Senior Engineer CAD Pre Silicon Front End
You will own front-end automation from RTL entry through DFT and implementation handoff. You will maintain design, verification, emulation, and FPGA prototyping flows; build AI-assisted tools; manage tool availability;…
RTL Designer
You will design, implement, and optimize RTL for core SoC components. You will collaborate on microarchitecture and hardware-software co-design, define hardware interfaces and execution flows, analyze performance…
Design Verification Engineer AI Accelerator
You will own verification of custom AI acceleration units, including matrix and vector compute engines. You will build test and coverage plans, develop reference models, verify numerical behavior and data flow,…
CAD Back-end Lead
You will build, integrate, qualify, release, and support CAD flows across custom design, physical implementation, and physical verification. You will develop reusable frameworks, automate regression testing and quality…
Senior Engineer CAD Pre-Silicon Front End
You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT…
Design Verification Engineer – AI Accelerator Lead
You will own verification for custom AI acceleration units, including matrix and vector compute engines. You will translate microarchitecture into test and coverage plans, build portable verification environments,…
Senior Design Verification Engineer – Physical AI Compute
You will develop and execute verification strategies for a Physical AI SoC, build SystemVerilog and UVM verification environments, define coverage goals, and verify compute engines, memory systems, interconnects,…
Principal AI SoC Runtime Software Architect
Own the software architecture for a heterogeneous AI SoC and define the end-to-end runtime across sensor ingest, preprocessing, AI inference, postprocessing, and application delivery. Coordinate workloads and data…
RTL Designer – Physical AI Compute
Design and optimize RTL for key portions of a Physical AI SoC, develop microarchitectures, define hardware interfaces and execution flows, contribute to compute and memory subsystems, optimize performance, power, and…
Performance Modeling Architect – AI Systems
Develop system-level performance models and simulation frameworks for AI workloads and compute architectures, modeling SoC components, software runtime behavior, memory systems, and interconnects to analyze…
Design Verification Engineer – Physical AI Compute
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Security Architect
Own the end-to-end security architecture for a Physical AI SoC, defining hardware roots of trust, secure boot, key management, secure debug, and lifecycle strategies. Protect AI workloads and sensitive assets, lead…
Power Management Architect, Physical AI SoC
Own the power architecture of a Physical AI SoC, defining power domains, voltage and frequency scaling, power states, power delivery, energy budgets, power-control subsystems, power intent, and power and thermal…
Functional Safety Architect
Own the functional safety architecture for a Physical AI SoC, defining safety goals, mechanisms, fault handling, quantitative metrics, RTL and firmware requirements, safety cases, certification, audits, and…
AI Systems Architect
Analyze modern AI model architectures, evaluate computational and system requirements, and map them to specialized hardware. Translate model requirements into efficient silicon implementations, optimize models and…
Physical Design Engineer (Staff / Sr. Staff / Principal)
Drive physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon, owning complex designs from RTL to GDSII across synthesis, floorplanning, place and route,…