Velaura AI, Inc.
Open positions
RTL Designer – Physical AI Compute
Design and optimize RTL for key portions of a Physical AI SoC, develop microarchitectures, define hardware interfaces and execution flows, contribute to compute and memory subsystems, optimize performance, power, and…
Performance Modeling Architect – AI Systems
Develop system-level performance models and simulation frameworks for AI workloads and compute architectures, modeling SoC components, software runtime behavior, memory systems, and interconnects to analyze…
Design Verification Engineer – Physical AI Compute
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Security Architect
Own the end-to-end security architecture for a Physical AI SoC, defining hardware roots of trust, secure boot, key management, secure debug, and lifecycle strategies. Protect AI workloads and sensitive assets, lead…
Power Management Architect, Physical AI SoC
Own the power architecture of a Physical AI SoC, defining power domains, voltage and frequency scaling, power states, power delivery, energy budgets, power-control subsystems, power intent, and power and thermal…
Functional Safety Architect
Own the functional safety architecture for a Physical AI SoC, defining safety goals, mechanisms, fault handling, quantitative metrics, RTL and firmware requirements, safety cases, certification, audits, and…
AI Systems Architect
Analyze modern AI model architectures, evaluate computational and system requirements, and map them to specialized hardware. Translate model requirements into efficient silicon implementations, optimize models and…
Director of Finance
Lead financial strategy, planning, budgeting, forecasting, accounting operations, reporting, cash flow, capital allocation, treasury functions, audits, tax filings, regulatory reporting, financial systems, growth…
Physical Design Engineer (Staff / Sr. Staff / Principal)
Drive physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon, owning complex designs from RTL to GDSII across synthesis, floorplanning, place and route,…
DFT Engineer Architect Manager Senior Manager
Lead Design-for-Test architecture, methodology, implementation, verification, and sign-off for complex ASIC and SoC designs. Drive test planning, pattern generation, coverage closure, memory and logic BIST strategies,…