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last month
CPU RTL Microarchitecture/Design Engineer - Full Time
HybridNorth AmericaFull-time
United States
What you'll do Design and implement CPU functional blocks based on microarchitecture specifications Develop, debug, and optimize RTL using SystemVerilog/Verilog Analyze performance, timing, area, and power tradeoffs…
Asic Automation C++ Perl Python +4 skills
last month
AI Accelerator RTL Microarchitecture/Design Engineer - Full Time
HybridNorth AmericaFull-time
United States
What you'll do Own the design and implementation of functional blocks within the accelerator pipeline Write and debug RTL (Verilog/SystemVerilog) for your assigned block Collaborate with verification engineers to…
Asic C++ Perl Python SystemVerilog +2 skills