AI Accelerator RTL Microarchitecture/Design Engineer - Full Time

What you'll do

• Own the design and implementation of functional blocks within the accelerator pipeline
• Write and debug RTL (Verilog/SystemVerilog) for your assigned block
• Collaborate with verification engineers to define test plans and close coverage
• Analyze performance, timing, and area tradeoffs and propose improvements
• Participate in design reviews and document your block's architecture and behavior

What we're looking for

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in computer microarchitecture, covering at least one of:
  • Cache/memory systems
  • Computer arithmetic
  • Pipeline design
• Working knowledge of a modern ISA
• Familiarity with parallel accelerator architectures, such as:
  • SIMD / SIMT / vector processing
  • Out-of-order scheduling
• Hands-on Verilog/SystemVerilog experience, including:
  • Simulation and testbench debugging
  • Timing and power closure
• Understanding of the end-to-end ASIC design flow and general VLSI concepts
• Scripting experience (Python, Perl, or Tcl); C/C++ a plus