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FuriosaAI

Systems Software Engineer NPU Management Interface

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Description

You will design and develop firmware and software for NPU management communication between hosts, BMCs, and NPU devices. You will implement management protocols and device-management features, integrate telemetry and health reporting, perform compliance and interoperability testing, and build validation tools.

Responsibilities

  • Design and develop NPU Management Interface firmware and software
  • Implement and maintain MCTP, PLDM, and custom management-interface command handling
  • Develop device-management features over SMBus, I²C, I3C, PCIe VDM, and sideband channels
  • Integrate health reporting, telemetry, utilization metrics, and debug information into NPU firmware
  • Perform specification-driven design, implementation, and validation
  • Support bring-up, interoperability testing, platform integration, and system-level validation
  • Develop test strategies and validation tools based on MCTP and PLDM specifications
  • Perform protocol compliance, regression, and interoperability testing

Requirements

  • Proficiency in embedded C or C++
  • Experience with firmware development for NPUs, accelerators, GPUs, or SoCs
  • Understanding of MCTP and PLDM
  • Experience with SMBus, I²C, I3C, SPI, and PCIe
  • Knowledge of embedded systems, bare-metal or RTOS environments, and firmware lifecycle flows
  • Experience with system-level debugging and low-level debug tools

Skills

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