SoC Subsystem Design Engineer

You will define SoC or subsystem architecture, create RTL designs, and integrate high-performance AI accelerator systems. You will coordinate IP integration with verification, software, and backend functions, work with DSP engineers, and lead silicon bring-up and hardware-software debugging. You will apply clock and power-control methods to improve robustness.

Responsibilities

• Lead SoC or subsystem architecture, RTL design, and system integration
• Coordinate IP integration with verification, software, and backend functions
• Collaborate with DSP engineers on hardware implementation of algorithms
• Lead silicon bring-up and hardware-software debugging
• Apply clock and power-control design methods to improve SoC robustness

Requirements

• At least 10 years of experience in high-complexity RTL design using SystemVerilog or Verilog
• Experience leading SoC subsystem designs from conceptual architecture through physical implementation
• Expertise with VCS or Xcelium for RTL and gate-level simulation debugging
• Mastery of Lint, CDC, RDC, DFT, synthesis, and IP-XACT integration flows
• Understanding of the full SoC lifecycle, including power-on reset sequences and clock-domain crossing