IP Design Engineer

You will define architectures and implement RTL for AI acceleration IPs and core SoC components. You will coordinate with verification, SoC integration, software, and DSP engineers, optimize hardware implementations of specialized algorithms, and participate in silicon bring-up and hardware debugging.

Responsibilities

• Define architecture and implement RTL for AI acceleration IPs and SoC components
• Coordinate with verification, SoC integration, and software functions
• Collaborate with DSP engineers to optimize hardware implementation of specialized algorithms
• Participate in silicon bring-up and hardware debugging

Requirements

• At least 3 years of RTL design experience using SystemVerilog or Verilog
• Experience from architecture definition through RTL implementation
• Proficiency with VCS or Xcelium logic simulation tools and RTL debugging
• Experience with Lint, CDC, DFT, and synthesis flows