Interconnect and Compute Architect

You will help define next-generation CPU networking architecture for datacenter and robotics applications. You will guide architectural decisions across forwarding, buffering, modeling, and RTL design, and collaborate to define networking requirements for AI and ML workloads.

Responsibilities

• Define next-generation CPU networking architecture
• Contribute to datacenter networking and robotics device specifications
• Guide architectural decisions across forwarding, buffering, modeling, and RTL design
• Collaborate to define and refine networking requirements
• Drive CPU networking architecture for AI and ML workloads

Requirements

• Knowledge of Ethernet network architecture and performance modeling
• Experience with die-to-die interfaces and associated protocols
• Understanding of on-chip and off-chip Ethernet fabrics
• Experience with UALink, NVLink, or Broadcom SUE
• Experience with RoCE, InfiniBand, or other scale-out RDMA protocols
• Eligibility to access U.S. export-controlled technology